In semiconductor devices, such as an IC and an LSI, a multilayer wiring structure is used for the purpose of dealing with the increase in length and in area of a wiring associated with the integration of various elements therein. In the semiconductor devices, in order to deal with higher integration, miniaturization of a wiring pattern is promoted to reduce a wiring cross-sectional area. On the other hand, in order to realize a high-speed operation, an electric current flowing through the wiring tends to increase. Thus, in the semiconductor devices, an electric current flowing through each wiring tends to increase in density.
The increase in electric current density in each wiring increases Joule heat production to cause various problems including deterioration of the wiring. Therefore, it is required to efficiently remove the heat produced in the wiring.
Further, an operation speed of the semiconductor device of the type is severely restricted by a product of a resistance value R of the wiring and a capacitance C attributed to the wiring, namely, an RC time constant. Hence, in order to increase the operation speed of the semiconductor device, it is required not only to reduce the resistance value R of the wiring, but also to reduce the capacitance C.
The problem as mentioned above exists not only in an individual semiconductor chip having a multilayer wiring structure, but also in a multilayer wiring structure of a semiconductor package on which the semiconductor chip is mounted. Further, the above-mentioned problem also exists in a substrate (a so-called printed board or the like) having the multilayer wiring structure on which a number of semiconductor devices are mounted, and in other multilayer wiring boards. That is, even in case where heat of the wiring is removed in the individual semiconductor chip and the resistance value R and the capacitance C of the wiring are reduced to increase the operation speed in the individual semiconductor chip, the operation speed is reduced as a whole and the problem due to heat can not be prevented if the multilayer wiring structure of the package or of the wiring board does not sufficiently address heat and has a large resistance value R and a large capacitance C.
In order to solve the above-mentioned problem, proposal has previously been made of a multilayer wiring structure in which, as an interlayer insulation film, a polymer material, such as SiO2, Si3N4, and polyimide, is used. The structure is provided with not only a through hole for interlayer electrical connection, but also a thermal via which is formed by filling a penetrating hole formed in the interlayer insulation film with an insulating material (AlN) having a thermal conductivity greater than that of the interlayer insulation film. Thus, interlayer heat conduction is carried out (for example, see Patent Document 1: Japanese Unexamined Patent Application Publication (JP-A) No. H9-129725).
Further, another multilayer wiring structure has previously been proposed in which, in order to further increase a signal transmission rate, air is used for interlayer insulation for the purpose of achieving a low-dielectric constant of an interlayer insulating portion (for example, see Patent Document 2: International Publication WO00/74135).
Patent Document 1: Japanese Unexamined Patent Application Publication (JP-A) No. H9-129725
Patent Document 2: International Publication WO00/74135